The invention relates generally to planarized interconnects for integrated circuit structures and more particularly to the formation of fully planarized interconnects.
U.S. Pat. Nos. 4,674,176 and 4,681,795 to Tuckerman describe thin film metal layer planarization processes for multilevel interconnect. In the fabrication of multilevel integrated circuit structures, the planarization of each metal layer eliminates irregular and discontinuous conditions between successive layers, particularly where vias are located.
The metal layer is planarized by heating for a brief, controlled time related to the spatial period of the features to be planarized. The entire planarization process, for forming the planarized interconnect, includes forming a thin film metal layer on a dielectric layer, and briefly heating the metal layer to produce a flat surface on the metal layer. An additional dielectric layer can then be deposited and the process repeated as many times as necessary to produce the required number of levels. However, in order to achieve fully planar multilevel interconnects, it is still necessary to planarize the dielectric layer.
Thus it is desirable to develop a planarization process in which dielectric planarization is unnecessary. This can be achieved by fabricating planarized metal interconnects which are flush with the dielectric layers. It is also desirable to develop a process in which further processing time is rapid and in which multiple interconnects can be processed simultaneously in a batch process.
A disadvantage of the planarization process, disclosed in U.S. Pat. Nos. 4,674,176 and 4,681,795, using pulsed laser or other heating, is the requirement of additional equipment and processing steps. It may be advantageous, in some circumstances, to form planarized structures without using the additional planarization apparatus or processing and/or without the associated heating, which may have a detrimental affect on various dielectric and other materials. Thus, it would be desirable to develop a process to form planarized circuit structures which eliminates the need for a separate planarization step for the metal layers, and which, in particular, eliminates the need for laser heating.